1. Field of the Invention
The present invention relates to non-volatile memory devices and, in particular, to a non-volatile memory which utilizes switching devices to permit segmentation of a memory "page" into multiple word lines.
2. Description of the Prior Art
Many non-volatile memories are organized in "X 8" configuration arrays, wit access to memory locations within an array provided on an individual byte basis. A group of bytes, commonly referred to as a "page" can be programmed simultaneously after data latches for an entire page have been sequentially loaded byte by byte. The number of bytes within a page normally is limited to the number of bytes along a word line or to a subset of such number.
The dimensions of a non-volatile memory array, particularly its aspect ratio (the ratio of length to width), determine the length of the word lines within a memory of a selected size, and thus set the maximum page size.
FIGS. 1A and 1B combine to show a typical prior art non-volatile memory array 10. The array 10 is "subdivided" into N sets of 8-bit bytes, i.e., Byte 1-Byte N in FIGS. 1A-1B, each byte including 8 bit lines. That is, Byte 1 includes bit lines 14-28, Byte 2 includes bit lines 30-44, and Byte N includes bit lines 46-60.
The array 10 further includes a plurality of word line running transverse to and intersecting the bit lines of the array 10 to define the memory cell locations of the array 10. For example, as shown in FIGS. 1A and 1b, one such word line, word line 12, intersects each set of bit lines 14-28, 30-44 and 46-60 to define corresponding memory locations 62-76 (as a first byte), 78-92 (as a second byte), and 94-108 (as a Nth byte), respectively. Those skilled in the an will appreciate that for purposes of illustration, only three bytes are described; however, additional bytes may be included within the memory array 10. The intersections of the multiple word lines and a common bit line define a column of memory cells locations in the array 10.
The array 10 also includes a first column-select line 110 that is connected in common to the gate of each of column-select transistors 112-126 associated with the Byte 1 bit lines 14-28. A second column-select line 128 is connected in common to the gate of each of column-select transistors 130-144 associated with the Byte 2 bit lines 30-44. Similarly, a Nth column-select line 146 is connected in common to the gate of each of column-select transistors 148-162 associated with the Byte N bit lines 46-60.
Referring now to FIGS. 1A and 1B and to FIG. 2, a byte latch 164 contained within and associated with Byte 1 contains eight separate data latches 166-180 (as illustrated in FIG. 2). Similarly, although not shown in FIG. 2, a byte latch 182 associated with Byte 2 and a byte latch 184 associated with Byte N, each contain eight separate data latches.
FIGS. 1A and 1B also show another of the plurality of word lines in the array 10, namely word line 186, intersecting the bit lines 14-60 to form memory locations 188-202 (as a first byte), 204-218 (as a second byte), and 220-234 (as an Nth byte). It is to be understood that although only two word lines 12 and 186 are illustrated, the bit lines 14-60 are typically associated with a number of word lines, generally groups of word lines with the group size being a power of two (2.sup.x). These additional word lines are represented in FIGS. 1A and 1B by the conventional "three dot" nomenclature shown between word 12 and word line 186. Thus, each of the individual data latches 166-180 of Byte 1 is associated with the selected memory location at the intersection of the selected word line and a bit line which is coupled to that particular data latch. Similarly, each of the eight separate data latches within each byte 182 and 184 is associated with corresponding multiple memory locations, although only two memory locations for each bit line are illustrated in FIGS. 1A and 1B.
In the operation of the array 10, a column-select signal applied to column-select line 110 turns on column-select transistors 112-126 to thereby connect bit lines 14-28 to input/output lines 236-250, respectively. An active load signal is provided to a strobe line 252 to simultaneously strobe the byte latches 164, 182 and 184 for Bytes 1, 2 and N, respectively. Since the active column-select signal is present only at column-select line 110 and not at column-select lines 128 and 146, a column-select gate ensures that data from the input/output lines 236-250 are loaded only into the byte latch 164 associated with Byte 1. The column-select signal is then removed from the first column-select line 110 and applied to the second column-select line 128, turning on column-select transistors 130-144 to thereby connect bit lines 30-44 to input/output lines 236-250. A load signal is again provided to strobe line 252 to simultaneously strobe byte latches 164, 182 and 184. A column-select gate within byte latch 182 ensures that data at the input/output lines 236-250 are loaded only into the byte latch 182 associated with Byte 2. This sequential loading continues until the column-select signal is applied to the Nth column-select line 146 to thereby turn on column-select transistors 148-162. Together with a load signal on the strobe line 252, this allows the loading of data from the input/output lines 236-250 into byte latch 184 associated with Byte N. Thus, data are sequentially loaded into the byte latches 164, 182 and 184 one byte at a time.
After all of the byte latches 164, 182 and 184 have been loaded and the column-select transistors 112-126, 130-144 and 148-162 are turned off, the word line 12 is selected and data within the byte latches 164, 182 and 184 are simultaneously programmed into memory locations 62-76, 78-92 and 94-108, respectively. The above sequence may then be repeated with new data which are sequentially loaded into each of the byte latches 164, 182 and 184. When the byte latches have been loaded and the column-select transistors 112-126, 130144 and 148-162 have been turned off, a different word line, for example word line 186, is strobed to thereby simultaneously program data from byte latches 164, 182 and 184 into the memory locations 188-202, 204-218 and 220-234, respectively.
The data stored at a given word-line location are referred to as a "page". The maximum page size (number of bytes at each word-line location) can be constrained by the physical dimensions of a memory array of a given size. The ratio of page size to number of pages (bit-line length) is limited by the manufacturability of integrated-circuit die with extreme aspect ratio (ratio of die width-to-length ratio). Therefore, it would be desireable to provide a method and apparatus which will not limit the selection of page length for a given total memory size.